A resin material is low in dielectric constant, good in flatness and high in transmittance, so it can be used as the material of insulating layers in an array substrate to reduce the capacitance among structures. However, the thickness of a resin layer is large, so the film thickness difference at a resin via hole is large as well, as a result, in the subsequent photolithographic process of the layers, photoresist at the resin via hole is thicker than that at other positions and thus is difficult to be removed completely, and film residue is liable to generate after etching to influence the product structure and cause poor display.
For example, FIG. 1 shows a diagrammatic drawing of an existing array substrate after pixel electrodes are formed. The pixel electrodes 19 in FIG. 1 are pixel electrodes of two adjacent sub-pixels, the pixel electrode 19 of an independent sub-pixel is located at the left side of a via hole 18, and the pixel electrode of another independent sub-pixel is located at the right side of the via hole 18, wherein a drain electrode 15 of a thin film transistor (sometimes called as “TFT” hereinafter) is located at the lower part of a resin layer 16, a passivation layer 17 is formed on the resin layer 16, and the via hole 18 (located in the resin via hole) needs to be formed in the passivation layer 17 by the photolithographic process, so as to connect the pixel electrode 19 on the passivation layer 17 with the drain electrode 15.
The first step of the above photolithographic process is to coat the photoresist, and as shown in FIG. 2, the thickness of the photoresist 10 at the resin via hole (2.2-4.2μm) is larger than the thickness of the photoresist 10 at other positions (1.3-1.5μm). When the photoresist is exposed through a mask plate 3, as shown in a figure on the left side in FIG. 3, the photoresist 10 in the resin via hole of a pixel region 1 is liable not to be completely removed due to insufficient exposure, while as shown in a figure on the right side in FIG. 3, the photoresist 10 in a non-pixel region 2 is fully exposed under the process condition and forms a corresponding shape; as shown in FIG. 4, in the subsequent etching process, the passivation layer 17 below the residual photoresist at the resin via hole is shielded, and thus cannot be completely etched, or cannot be etched at all, resulting in that the via hole of the passivation layer 17 is too small or absent. When the via hole of the passivation layer 17 is absent, the pixel electrode located on the passivation layer 17 cannot be connected with the drain electrode, so the pixel cannot emit light, resulting in poor display.
Similarly, as shown in FIG. 5, when the pixel electrodes 19 are formed, if the photoresist 102 in the resin via hole cannot be completely removed, the material of a part of pixel electrodes cannot be removed, such that the pixel electrodes 19 in the adjacent sub-pixels are connected, and independent pixel electrodes 19 (as shown in FIG. 6) cannot be obtained.
It is well known that the array substrate may further include a thin film transistor (not shown in the figure), a substrate, a gate insulation layer, a gate electrode and other structures.